The present invention relates to a memory circuit, and more particularly a semiconductor memory circuit employing MOS transistors.
In semiconductor memory is making use of MOS transistors, the memory capacity has been steadily increasing owing to the progress of the integration technique in the recent years and memory devices having 64 K bit capacity have been made commerciably available. While, owing to the progress of the circuit technique, the number of pins in a package has been decreased and the integration density of memory devices has been increased by a multiple-addressing technique this technique is detailed in U.S. Pat. No. 3,969,706 in which row address signals and column address signals are incorporated through the same set of address terminals in response to a row address strobe signal (RAS) and a column address strobe signal (CAS), respectively. However, according to the multiple-addressing technique, each operation of the memory requires the activation of the row address strobe signal and the activation of the column strobe signal in sequence, and hence the operation speed of this type memory has been limited. In this respect, the inventor of the present invention has already proposed a novel memory in Japanese patent application No. 100850/1980 which has now issued as U.S. Pat. No. 4,429,375. According to this prior application, the memory circuit is a MOS random access memory (hereinafter abbreviated as RAM) formed by providing a plurality of input/output (I/O) bus pairs and a decoder circuit associated with a shift register for enabling the I/O bus pairs to access consecutive addresses along the column direction thereof. The RAM is addressed according to the multiple-addressing system employing a Row Address Strobe clock (RAS) and Column Address Strobe clock (CAS), in which initially any arbitrary address information is taken in upon the normal RAS/CAS cycle. When the memory cell has been accessed, column address information is taken in the shift register at the same time. Thereafter, when the operation is transferred to a "consecutive access mode" which is controlled only by the CAS clock while maintaining the RAS clock at its active level, memory cells having consecutive addresses along the column direction, which addresses are determined on the basis of the column address information taken in during the RAS/CAS cycle just before the transfer to the consecutive access cycle, are accessed bit by bit with each CAS clock signals as controlled by a shift clock generated during the consecutive access mode. Therefore, access can be performed without necessitating the column address information which was obtained through a column address buffer in the prior art, so that the operation time necessitated therefor can be omitted.
In connection with the access time in the above-described operation mode, in addition to not necessitating the above-mentioned column address information, the data of the memory cells in the accessed row have already been transmitted to a plurality of I/O bus pairs in amplified states, so that the I/O bus pairs are sequentially selected by an internal clock which is generated immediately at the falling edge of the CAS clock. Only a data buffer amplifier associated with the I/O bus pair is activated by a clock generated subsequently in response to the internal clock, and it can transmit cell information to an output terminal. Accordingly, a remarkable effect can be achieved such that high speed access, which has not realized in the page mode in the prior art, can be achieved. As described above, the access time in this consecutive mode is as short as 30 NS or less, the cycle time including the reset time of the CAS is also short as 70 NS or less, and thus a memory circuit operable at a high cycle speed can be realized. However, during a write cycle in the consecutive access mode, the operations of taking input information into a data input buffer, producing data binary codes, transferring data to a selected memory cell, etc. must be completed within the activation period of the CAS, but it is definitely impossible to finish these various operations within the very short period of 30 NS or less. Hence, it is necessary to increase the CAS activation period by about 20 NS. This results in a large difference between the read cycle time and the write cycle time, and disadvantages may possibly occur such as a difficulty in the control for the generation of an external drive clock, or a degradation in performance upon introducing the RAM into a system.